Planar Double-Gate Transistor: From technology to circuit by Amara Amara, Olivier Rozeau

By Amara Amara, Olivier Rozeau

This e-book on Double-Gates units and circuit is exclusive and goals to enhance the synergy among the study actions on CMOS sub-32nm units and the layout of common cells. The objective is to indicate how we will reap the benefits of new transistor buildings to return up with new simple cells and ideas that make the most good points of those new units and the leap forward they bring.

Planar Double-Gate Transistor will frequently specialize in SOI CMOS transistors, absolutely depleted with double self sustaining planar Gates (Independent Planar Double Gates Transistors: IPDGT), a possible candidate for the sub-32 nm technological nodes as deliberate by way of the present ITRS Roadmap.

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Doczy, J. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios and R. Chau, “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout”, in Technical Digest of IEEE Symposium on VLSI Technology, pp. 133–134, Kyoto, Japan, June 2003. 41. J. T. Park, J. P. Colinge and C. H. Diaz, “Pi-Gate SOI MOSFET”, IEEE Electron Device Letters, vol. 22, no. 8, pp. 405–406, August 2001. 42. F. L. Yang, H. Y. Chen, F. C. Chen, C. C. Huang, C. Y. Chang, H. K. Chiu, C. C. Lee, C. C. Chen, H. T. Huang, C.

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