New Information Technology and Participation in Europe 2000 by D. Frohlich, D. Fuchs, H. Krieger

By D. Frohlich, D. Fuchs, H. Krieger

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5. 1 Advanced LS Is; The logic circuits are designed using high-speed, high-density emitter-coupled-logic (ECL). Each ECL LSI can pack 15000 of 80 ps delay gates. 6 nano seconds access time are packed with 3500 logic gates together on the same chip. For the main storage, 1M-bit large-capacity static random access memory chips with 35 nano seconds access time were adopted. 37 Pig . 2 High Density Packaging; Pujitsu is the first to have introduced glass ceramics as a board material for greater transmission speed.

1 --------- veclOr 84 t- + + + ~ H--1'_--1'--1'--1 2 1I n ) + ) (0) single pipeline 5 I R 6 2 H 7 3 I=l vector output vector r r r ----- 3 -2 ----- 0-1 t- • 5 1 6 2 7 3 8 4 (bl parollel pipeline input vector output vector O°--f' 0-) . ~-z -I --- ------- + 5 I ~ 6 2 ~ t- ---1 t- 7 3 8 4 ~ + ~-) -2 . n-I '-- ----- -- -- (el multiple-porallel pipeline Fig. 9. J) II 0 0 o 0 Distonce (3) LISt (,nd,rect) vector doto IX(I) Index list AOX(i)) (4) )' 0 • \ " I ----------- ~ b -- ----- 0 Vector compression A Vector mask 8 (5) Vector exponson A Vector mask I I , 8 (6) Vector mask operations F·-·F·' A + 8 Vector mask C I I ( 0,+ .

Each frame has a unique frame name and consists of a set of slots as components which store attribute data associated to the frame. , a slot name, a datatype specification, slot value(s), demon(s), and an option. 4 A new modeling method of representing an arch in an extended frame representation scheme. 5 HEIGHT LENGTH WIDTH FUNCTION VALUE VALUE VALUE TEXT PhyslcalObJect A,B,C (SUPPORT B A), (SUPPORT C A), (RIGHTOF C B), (MUSTNOTTOUCH B C) NIL(Default 10) NIL(Default 10) NIL(Default 5) Toy FRAME: ISA HASPARTS Arch-X FRAME FLIST (a b c) Arch An example of frame descriptions for Arch and Arch-X according to the concept of the object model.

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