Hardware/Software Co-design for Heterogeneous Multi-core by Koen Bertels (auth.), Koen Bertels (eds.)

By Koen Bertels (auth.), Koen Bertels (eds.)

HW/SW Co-Design for Heterogeneous Multi-Core structures describes the consequences and consequence of the FP6 venture which makes a speciality of the advance of an built-in software chain focusing on a heterogeneous multi middle platform comprising of a normal function processor (ARM or powerPC), a DSP (the diopsis) and an FPGA. The instrument chain takes current resource code and proposes variations and mappings such that legacy code can simply be ported to a latest, multi-core platform. Downloadable software program may be supplied for simulation purposes.

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These should be hexadecimal number and thus you must use “0x” prefix. • END_ADDRESS: is the ending range of memory addresses in the shared memory. These should be hexadecimal number and thus you must use “0x” prefix. 20 A. Lattanzi et al. Example: MEM1 SDRAM 128 0 0xFFFFFFFF The BUS_COMPONENT contains: • NAME: used to identify the bus. • BANDWIDTH: the size of one memory transfer in kbytes/sec (for example: 1024).

Lattanzi et al. , C functions) and implementations; • PROFILES: which contains additional information generated by tools. ... ... ... The HARDWARE XML Element The HARDWARE element contains the following elements: • • • • • NAME: name of the board/hardware; FUNCTIONAL_COMPONENT: which describes each processing element; STORAGE_COMPONENT: which describes the storage (memory) elements; BUS_COMPONENT: which describes architectural interconnection elements; VBUS_COMPONENT: which describes virtual (direct) interconnection elements.

If the functional component is not FPGA, this can be omitted. Example: SAD Arm 11 100 3 10 0X00000000 0X00000000 100 200 In the presented Architecture Description File, there is a clear delimitation about the hardware/software features of the target architecture/application.

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