FPGA Architecture by Ian Kuon, Russell Tessier, Jonathan Rose

By Ian Kuon, Russell Tessier, Jonathan Rose

Field-Programmable Gate Arrays (FPGAs) became one of many key electronic circuit implementation media over the past decade. an important a part of their production lies of their structure, which governs the character in their programmable good judgment performance and their programmable interconnect. FPGA structure has a dramatic influence at the caliber of the ultimate device's velocity functionality, region potency and gear intake. FPGA structure: Survey and demanding situations studies the historic improvement of programmable common sense units, the elemental programming applied sciences that the programmability is outfitted on, after which describes the elemental understandings gleaned from examine on architectures. FPGA structure: Survey and demanding situations begins with a short review of programmable common sense to supply a context for the next sections which overview the heritage of programmable common sense, and the underlying programming applied sciences. the subsequent sections outline the terminology of FPGA structure, after which describe foundations and traits of good judgment block structure and routing structure together with a dialogue of strength administration recommendations and similar circuit layout matters. a short evaluation of the input/output constructions and architectural questions in FPGAs is then awarded through an particular comparability among FPGAs and competing ASIC general cellphone expertise. It concludes with a assessment of a few of the layout demanding situations dealing with FPGAs and a glance at rising architectures for FPGAs. FPGA structure: Survey and demanding situations is a useful reference for engineers and desktop scientists. it's also a great primer for senior or graduate-level scholars in electric engineering or machine technology.

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FPGA Architecture

Field-Programmable Gate Arrays (FPGAs) became one of many key electronic circuit implementation media over the past decade. a very important a part of their construction lies of their structure, which governs the character in their programmable good judgment performance and their programmable interconnect. FPGA structure has a dramatic impact at the caliber of the ultimate device's velocity functionality, zone potency and gear intake.

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A device family typically consists of a set of FPGAs with the same basic architecture that contain differing amounts of resources. For example, devices in the Lattice EPC2 family are available in six sizes including devices with between 6,000 LUTs and 68,000 LUTs [124]. A designer can select the device with the most appropriate ratio, minimizing “wasted” computational tiles. The cost of this flexibility is incurred by the FPGA vendor, who must support a larger number of devices. This concept works against the fundamental economies of a single family serving many applications.

3 Computation-Oriented Tiles An early example of a computation-oriented tile is the multiplier integrated into the Xilinx Virtex II FPGA [229]. This tile consisted of an 18 × 18 2’s complement multiplier that sat alongside a block memory tile. Since the introduction of the Virtex II, Xilinx and other manufacturers have introduced more sophisticated hard computational units that include multiplier-accumulators, and some multiplexer functions [228, 231]. 8 Heterogeneity 35 larger multipliers into groups of smaller multipliers.

Fig. 6 Example channel segmentation distribution [37]. 52 Routing Architecture The need for a mix of segment lengths in island-style FPGA devices is motivated by the characteristics of benchmark designs targeted to the devices. The amount of interconnect required by a circuit has been found to be related to Rent’s rule [123], a well-known relationship between the size of a group of logic and the number of its external connections. This relationship indicates that the amount of pins, P , needed for an amount of logic, G, grows as P = K × GB , where B is a parameter known as Rent’s exponent and K is a scaling constant.

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